1. Field of the Invention
The present invention relates to semiconductor circuit fabrication and, more particularly, to a circuit and a method of forming the circuit that has a subsurface network of conductive paths within a silicon substrate.
2. Description of the Related Art
Integrated circuit fabrication involves creating various semiconductor devices such as transistors, capacitors, resistors, and diodes within a single monolithic semiconductor substrate. Traditionally, a number of photolithographic and ion implantation steps are required to form the semiconductor devices.
In addition, to complete the circuit, conductors are formed to electrically connect the isolated devices together. A number of additional photolithographic steps are required to form the conductors that are required to connect the devices together to implement the circuit.
A typical method of providing conductive paths between devices is to form conductive interconnects on top of the silicon substrate using patterned layers of metal (or metal silicide or polysilicon). Interconnects created in the metallization process can be formed in multiple layers, by alternating metal layers with intermetallic dielectric (IMD) layers.
The IMD layers serve to electrically isolate the metal layers. The IMD layers are patterned to allow formation of vertical conductors between metal layers and devices, through use of a system of contacts and vias, or plugs. A multilevel interconnect system as described, can be used to create multiple conductive paths in three dimensions. It also allows conductors to be arranged to pass over or under adjacent conductors while remaining isolated from each other.
The cost to produce a semiconductor circuit is in large part defined by the complexity and number of photolithographic and ion implantation steps that are required to fabricate the circuit. As a result, as the complexity and number of steps required to fabricate the circuit increase, the cost to fabricate the circuit increases as well.
Thus, there is a need for a method of forming interconnects and devices, such as transistors, that reduces the complexity and/or number of photolithographic and ion implantation steps that are required to fabricate the interconnects and transistors of a circuit.